In this section of the guide, we’re going to build a simple half adder using the CPLD. If you don’t know what a half adder is, or even a full adder, take a look here. The half adder will introduce two new logic gates, the XOR gate and the AND gate.
Basically, we’re going to add binary bits together.
Let’s get started by taking a quick look at the logic diagram for the half adder. We start off with two inputs which are either on or off (0 or 1). Because we’re working with binary numbers, if you add 01 and 01 together you end up with 10. There are plenty of great youtube videos available that will explain this very well.
After the maths has been done in logic, we have two output LEDs which show the sum of the inputs and a carry.
Once you’ve built, compiled and uploaded your design to your CPLD, it’s time to build the hardware. you’ll want to follow the schematic shown to the right. This should be simple enough if you’ve completed Part 4 of the guide.
When you connect your CPLD to your newly built hardware, have a play with the switches. You should see that if one and only one of the switches is on, one LED will light up. This should be true which ever switch you turn on. If you turn both switches on, the first LED will turn off and the second LED will turn on.
I’ve added some pictures of a quick build I did. Excuse the messy wiring. I’ve also opted to use a bar graph LED display and a multi jumper switch but normal LEDs and switches will work perfectly.
There you have it, you’ve built a half-adder using logic gates in a CPLD chip.
Stay tuned for Part 6.
Other articles in this series can be found here.