It’s a very simple modification to the schematic design. We simply invert the B inputs and leave the A inputs as they are. Instead of adding A and B, this configuration will subtract B from A.
Another thing we need to do is to is think about the carry-out bit. If we were working with 1s compliment, we would feed the carry-out back round to the carry-in. This isn’t the best option for our circuit, it would be far better for us to use 2s compliment. Using 2s compliment, we simply feed a 1 into the first carry-in.
To do this, we change the carry-in GND to a VCC to make it high.
For a much better explanation of all of this, I recommend watching this youtube video. This is a great tutorial about binary subtraction and will go into far greater detail than I will here.
The last thing we need to do is change the carry-out bit to a GND instead of a pin header. This will stop the 5th bit LED from lighting up.
Once you’ve modified your design, compile and upload to your CPLD chip.
Now you have a 4-bit binary subtractor.
I haven’t gone into much detail here about the way binary subtraction works. These guides are more focused on the CPLD side of things but the video I linked to earlier really is essential viewing material to fully understand why our design works.
In the next article, we’re going to combine our adder, subtractor and a multiplexer to create a fully functional arithmetic logic unit or ALU.
Other articles in this series can be found here.